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All other basic functions (lw, sw, lui, beq, bne, j) will be implemented as show in the textbook.
The processor will have two main stages: load instructions into memory and execute instructions. Special instruction codes will be defined as "stall" and "stop execution" to work in conjunction with the FSM. The global reset will set all memory and registers to 0, and put the FSM in "load instructions mode". We would like to use one memory module to store both instructions and data (with instructions starting at 0 and going up, and memory starting at the highest address and going down), however this design would present some addressing headaches so we will most likely use separate memory modules for instructions and data...
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